This invention relates in general to semiconductor memories and, in particular, to the design, operation, and testing of multilevel nonvolatile semiconductor memories.
Testing multilevel nonvolatile memories poses new problems which are not encountered in either single-bit per cell memories or in analog memory storage architectures.
A first problem deals with detecting and screening out cells which program more than intended. To obtain the programming precision required for multilevel cells, iterative programming algorithms have been used. These algorithms execute a verify step followed by a programming pulse step if necessary (a sensing step performed during a programming algorithm is called a verify step, while a sensing step performed subsequent to the programming algorithm forms part of a read operation). The verify program iteration is repeated until the desired charge storage level in the cell is reached with the required precision. During a programming iteration, the amount of charge in the cell is incremented in small amounts so as not to overshoot the desired level. The data stored will be incorrect if a cell programs too much and overshoots the desired level. The overshoot problem poses additional detection problems when the iterative programming algorithm (technique) is used. This will be described in more detail later.
A second problem encountered in multilevel nonvolatile memories is the ability to economically test whether each memory cell in a large array of cells arranged in rows and columns receives the proper control signals for reliable multilevel operation. For example, every column and row driver circuit needs to be efficiently tested for functionality and defects such as shorted or open rows or columns need to be efficiently detected. In single-bit per cell memory, a common way to determine whether the rows and columns of cells function properly is by using such conventional programming patterns as checkerboard data patterns.
The checkerboard data pattern refers to data programmed in physical cell locations such that each programmed cell has an erased cell on adjacent orthogonal row and column locations. Programmed cells are located on diagonal adjacent locations. Defect determination is made after the data is programmed. If the data subsequently read out of the chip fails to verify to the expected checkerboard data pattern, a defect is found.
In single-bit per cell memories, the functionality determination involves only two levels per cell (i.e., programmed data level and erased data level), and the use of the checkerboard pattern is quite appropriate. In multilevel memories however, the checkerboard data pattern is insufficient to determine if the array is fully functional since the data is not restricted to just 2 levels. In multilevel operation, each memory cell will contain 2N levels of information, where N is the number of digital bits stored in each cell. In the examples used to describe different embodiments of this invention, 4 bits are stored per cell requiring 16 levels. Testing all 16 levels for each memory cell would fully test the multilevel functionality of the chip but would take too long and raise test and chip cost.
A third problem is the ability to properly test the cells"" sensing margin. The sensing is partly accomplished by comparing a voltage value VR generated by the selected memory cell on a column to which it is coupled to a selected one of a plurality of reference voltage values. The sensing margin is defined as the difference between the VR value and the selected reference value. If the sensing margin becomes too small, the sensing circuits may not sense the data properly over the chip""s specified operating temperature and power supply voltage ranges. In addition, during testing of a memory chip, voltage and/or temperature stress conditions are applied which may reduce the sensing margin in certain cells, thus allowing these cells to be identified as potentially unreliable. In multilevel memories, the separation between reference values become quite small for larger N values, e.g., for N greater than 2. For instance, the separation between adjacent reference values which form the boundaries for each valid data range may be less than 100 mV for a 4-bit multilevel system (i.e., N=4,) but 400 mV for a 2-bit system for the same cell technology. Thus, the relatively small sensing margin for systems with N greater than 2 requires special new testing techniques and circuitries.
Thus, new testing methodologies and circuit techniques will be described which address the above-identified problems as well as other problems encountered in testing multilevel nonvolatile memories. Also, new margin testing techniques which speed up multilevel cell testing will be described.
In accordance with an embodiment of the present invention, a method for testing a multilevel memory includes: performing an erase operation to place a plurality of memory cells in an erased state; programming a state of each cell in a group of the plurality of cells to within a first range of voltages; if a state of each of one or more of the cells in the group of cells does not verify to within the first range of voltages, identifying at least the one or more cells as failing; and if a state of each cell in the group of cells verifies to within the first range of voltages: applying a predetermined number of programming pulses to further program the state of each cell in the group of cells to within a second range of voltages; and verifying whether a state of each cell in the group of cells is programmed beyond the second range of voltages.
In another embodiment, the method further includes: if a state of each of one or more cells in the group of cells is programmed beyond the second range of voltages, identifying at least the one or more cells as failing.
In another embodiment, if a state of each cell in the group of cells verifies to within the first range of voltages, no verify operation is performed before or during the applying step.
In another embodiment, the first range and the second range are two of a plurality of sequentially defined voltage ranges which start with an initial range corresponding to the erased state, the first range being one of a first group of the plurality of sequentially defined voltage ranges substantially close to the initial range.
In another embodiment, each of the plurality of sequentially defined voltage ranges corresponds to one of a plurality of distributions of sensing voltages generated by the memory cells. Each of the plurality of sequentially defined voltage ranges is within a corresponding larger range of voltages, each larger range corresponding to one of 2N binary combinations of N bits of data capable of being stored in each cell, wherein N is a positive integer. The larger ranges are non-overlapping.
In accordance with another embodiment of the present invention, a multilevel memory has an array of erased memory cells arranged along rows and columns, each cell being capable of storing N bits of data by setting a state of each cell to within one of 2N voltage ranges, the cells along each row being divided into M groups, each of the M groups having a plurality of adjacent memory cells, N and M being integers greater than 1, wherein in a memory access one of a plurality of pages of memory cells in a row is selected, each page having M memory cells, one cell from each of the M groups of cells, a subset of each page of M memory cells comprising 2N cells. A method for testing such a multilevel memory includes: programming a state of each cell in a first group of 2N cells located along each column to a respective one of the 2N voltage ranges; and programming a state of each cell in a second group of cells comprising the 2N cells in the subset of a selected page along each row, each of the 2N cells in the subset of the selected page along each row being programmed to a respective one of the 2N voltage ranges.
In another embodiment, the method further includes: programming a state of each of 2N reference cells along each row to a respective one of the 2N voltage ranges; and comparing a state of each of the 2N cells in the subset of the selected page along each row to a state of a corresponding one of the 2N reference cells along the same row.
In another embodiment, each of the M groups of cells comprises K adjacent memory cells, there being K pages of memory cells along each row, and the method further includes: programming a state of each of the 2N cells in the subset of each of the K pages along each row to a respective one of the 2N voltage ranges.
In another embodiment, the multilevel memory further comprises K groups of reference cells along each row, each of the K groups of reference cells comprising 2N reference cells, and the method further includes: programming a state of each of the 2N reference cells in each of the K groups of reference cells along each row to a respective one of the 2N voltage ranges; and comparing a state of each of the 2N cells in each of the K subsets along each row to a state of a corresponding one of the 2N reference cells in each of the K groups of reference cells along the same row.
In another embodiment, the first group of cells are located substantially along a first side of the array furthest from a column select circuit coupled to the columns, and the second group of cells are located substantially along a second side of the array furthest from a row select circuit coupled to the rows.
In accordance with another embodiment of the present invention a multilevel memory has an array of erased memory cells, each cell being capable of storing N bits of data by setting a state of the cell to within one of 2N voltage ranges, each of the 2N voltage ranges comprising a distribution voltage range and at least one margin voltage range, N being an integer greater than 1. A method of testing such multilevel memory includes: programming a state of each of a plurality of the memory cells to within the distribution voltage range of at least one of the 2N voltage ranges; sensing the state of each of the plurality of programmed memory cells; and identifying any of the programmed memory cells whose state resides within the at least one margin voltage range, wherein a magnitude of the at least one margin voltage range is adjustable.
In another embodiment, the memory is an integrated circuit, and the method further includes: internally generating a plurality of predefined margin voltage values used to define a magnitude of the at least one margin voltage range of each of the 2N voltage ranges; and externally selecting at least one of the plurality of predefined margin voltage values for defining a magnitude of at least one margin voltage range of at least one of the 2N voltage ranges, wherein the internally generated plurality of predefined margin voltage values are adjustable.
In another embodiment, each of the 2N voltage ranges comprises an uppermargin voltage range and a lower-margin voltage range, and the method further includes: identifying any of the programmed memory cells whose state resides within either the upper-margin voltage range or the lower-margin voltage range, wherein the upper-margin voltage range and the lower-margin voltage range of each of the 2N voltage ranges are adjustable.
In accordance with another embodiment of the present invention, a multilevel memory has an array of erased memory cells, each cell being capable of storing N bits of data by setting a state of the cell to within one of 2N voltage ranges, each of the 2N voltage ranges comprising a distribution voltage range and at least one margin voltage range, N being an integer greater than 1. A method of testing such multilevel memory including: setting the distribution voltage range of at least one of the 2N voltage ranges to a smaller range than a corresponding distribution voltage range used during normal memory programming mode; programming a state of each of a plurality of the memory cells to within the distribution voltage range of the at least one of the 2N voltage ranges; subjecting the plurality of programmed cells to stress conditions; and if a state of one or more of the programmed cells drifts a predetermined amount out of the smaller distribution voltage range, identifying the one or more of the programmed cells.
In another embodiment, the smaller distribution range is obtained by setting a magnitude of the at least one margin voltage range to be greater than a magnitude of the corresponding margin voltage range used during normal memory programming mode.
In another embodiment, the memory is an integrated circuit, and the predetermined amount corresponds to a tolerated-drift voltage range. The testing method further includes: internally generating a plurality of predefined tolerated-drift voltage values used to define a magnitude of the tolerated-drift voltage range of the at least one of the 2N voltage ranges; and externally selecting at least one of the plurality of predefined tolerated-drift voltage values for defining a magnitude of the tolerated-drift voltage range of at least one of the 2N voltage ranges.
In accordance with another embodiment of the present invention, a multilevel memory has an array of erased memory cells, each cell being capable of storing N bits of data by setting a state of the cell to within one of 2N voltage ranges, N being an integer greater than 1. A method of testing such multilevel memory including: dividing the 2N voltage ranges into at least a first group of one or more voltage ranges and a second group of one or more voltage ranges; programming a state of each of a plurality of the memory cells to within the second group of one or more voltage ranges; sensing the state of each of the plurality of programmed memory cells; and identifying any of the programmed memory cells whose state resides within the first group of one or more voltage ranges as failing.
In another embodiment, the 2N voltage ranges are sequentially defined between a first voltage range corresponding to an erased state and a 2N voltage range corresponding to a highest programmed state.
In another embodiment, the method further includes: generating a plurality of reference voltages for uniquely identifying each of the 2N voltage ranges; and forcing all the plurality of reference voltages to be equal to a mid-reference voltage between the first voltage range and the 2N voltage range.
In another embodiment, the method further includes: generating a mid-reference voltage, the mid-reference voltage being substantially near a center of the sequentially defined 2N voltage ranges, voltage ranges above the mid-reference voltage corresponding to the first group of one or more voltage ranges, and voltage ranges below the mid-reference voltage corresponding to the second group of one or more voltage ranges.
In another embodiment, the method includes: generating a mid-reference voltage, the mid-reference voltage being substantially near the 2N voltage range, voltage ranges above the mid-reference voltage corresponding to the first group of one or more voltage ranges, and voltage ranges below the mid-reference voltage corresponding to the second group of one or more voltage ranges.
In another embodiment, the method includes: generating a first reference voltage and a second reference voltage dividing the 2N voltage ranges into three groups of voltage ranges, a first one of the three groups of voltage ranges corresponding to the first group of one or more voltage ranges and being between the first and second reference voltages, a second one of the three groups of voltage ranges corresponding to the second group of one or more voltage ranges and being below the second reference voltage, a third one of the three groups of voltage ranges being above the first reference voltage.
In another embodiment, the sensing step comprises N or more sensing cycles, and the method further includes: generating a plurality of reference voltages for uniquely identifying each of the 2N voltage ranges; during a plurality of the N or more sensing cycles, forcing the plurality of reference voltages to be equal to a mid-reference voltage between the first voltage range and the 2N voltage range; during one of a remaining sensing cycles, forcing one of the plurality of reference voltages to be equal to the first reference voltage; and during another of the remaining sensing cycles, forcing another of the plurality of reference voltages to be equal to the second reference voltage.
In accordance with another embodiment of the present invention, a multilevel memory includes: an array of memory cells each being capable of storing N bits of data by setting a state of the cell to within one of 2N voltage ranges, N being an integer greater than 1; and a first circuit configured to receive a plurality of reference voltages and one of a plurality of predefined margin sensing voltages, the plurality of reference voltages uniquely identifying each of the 2N voltage ranges, the first circuit performing an arithmetic operation on the reference voltages and the one of the plurality of predefined margin sensing voltages, and providing a modified plurality of reference voltages for use in sensing operations.
In another embodiment, the memory further includes: a reference voltage generator configured to generate the plurality of reference voltages; and a precision margin generator configured to generate the one of the plurality of predefined margin sensing voltage values.
In another embodiment, the reference voltage generator includes: a reference circuit for generating a first set of reference voltages; a plurality of reference memory cells for generating a second set of reference voltages; and a multiplexer for selecting one of the first and second sets of reference voltages as the plurality of reference voltages for transfer to the first circuit.
In another embodiment, the multiplexer is configured to force a predetermined number of the selected one of the first and second sets of reference voltages to a predetermined subset of the selected one of the first and second sets of reference voltages.
In accordance with another embodiment of the present invention, a multilevel memory includes: an array of memory cells each being capable of storing N bits of data by setting a state of the cell to within one of 2N voltage ranges, N being an integer greater than 1; and a first circuit configured to receive a plurality of reference voltages uniquely identifying each of the 2N voltage ranges, the first circuit being capable of reconfiguring the plurality of reference voltages to reduce the 2N voltage ranges to less than 2N ranges so that the storage capability of each cell is reduced from storing N bits.
In another embodiment, the multilevel memory is a nonvolatile memory and is an integrated circuit, each of the 2N voltage ranges has a magnitude less than 150 mV, and N is greater than 2.
The circuits and testing methodologies of this invention can be used in the field to ensure the reliable operation of a multilevel memory system.
The following detailed description and the accompanying drawings provide a better understanding of the nature and advantages of the present invention.